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Gated Clock-Practical Study

Gated Clock-Practical Study

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Gated Clock - Practical Study

2010 Nian 7 Yue 3 Ri 

4bit with enable counter, including positive edge trigger and negative edge trigger;

1. Functional simulation:

1. Circuit structure and simulation waveform:

 xb

 

xb

2. Insert belt latch of the ICG (Integrated gating):

1. Comprehensive script:

 xb

2.  Gated comprehensive results:

 xb

3. Simulation waveform:

xb 

3. Insert without the latch of the ICG :

1. Comprehensive script:

1. Need to find if there is ICG without Latch in thelibrary;

2. Need to select the corresponding gating unit of the rising edge trigger register and the falling edge trigger register;

3. Script:

 

 

2. Comprehensive results:

 

 xb

 xb

 

3. Simulation timing diagram:

 xb

 

4. Note:

1. Enable with rising edge output (this enablement can be made by combining the rising edge signal output by a clock). Registers that control the rising edge can be inserted into the ICG of the rising edge type;

2.只有下降沿输出的使能(这个使能只要是通一个时钟输出的上升沿信号组合出来的都可以)控制下降沿促发的寄存器才可以插入下降沿类型的ICG

3.如果要使用上升沿组合成的使能来门控下降沿的门控或反之,则需要手工例化ICG,或写门控逻辑来门控。

4. 如果在综合脚本改成下面的脚本,综合会保持,结果会插入带latch结构的ICG

 

 xb

 

4.插入带latch的分立门控:

1.门控综合脚本:

 xb

 

2.门控综合结果:

 xb

 

3. 仿真波形:

 xb

 

5. 插入不带latch的分立门控:

1.综合脚本:

 xb

 

2.综合结果:

 

 xb

 xb

 

3.仿真波形:

 xb

 

4. 注意点:

1.只有上升沿输出的使能(这个使能只要是通一个时钟输出的上升沿信号组合出来的都可以)控制上升沿促发的寄存器才可以插入上升沿类型的CG

2.只有下降沿输出的使能(这个使能只要是通一个时钟输出的上升沿信号组合出来的都可以)控制下降沿促发的寄存器才可以插入下降沿类型的CG

3. If you want to use the enable combination of rising edges to gate the falling edges or vice versa, you need to manually instantiate CG or write the gate logic to sequence.

 

6. Remaining issues

1. Gated cell selection plus path look.

2. Does DC guarantee that En is between the rising and falling edges?

 

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