
NEWS CENTER
Gated Clock-Overview
Gated Clock-Overview
Gated Clock - Overview
February 12, 2009
1. Clock signal power consumption accounts for a large part of the system power consumption ( about 40% ) and accounts for more than 50% of dynamic power consumption
1. DC gated clock command:
intert_clock_gating
set_clock_gating_style
1. Gated clock insertion:
1. Use effect examples:
a. For a 180nm chip technology: has clock gating and no clock gating results in comparison (chip Found):
a. Power saving of 34% to 43% (more specific application mode)
a. Area saving 20% (a clock gating can replace multiple mux )
1. Principles of use:
a. Registers with a bit width of 3 or more must use a gated clock
a. The use of a gated clock for a single- bit register has no effect, and neither area nor power consumption will be saved.
a. Clock buffer尽可能多的放到clock gating cell的后面。
1. RTL具体措施:
a. 无用输出采用使能保持输出的方式编码:
NxtReadData = (ReadEn) ? RamData : 8'b0;
如果没有读使能时,我们不关心输出什么数据的话,则改成:
NxtReadData = (ReadEn) ? RamData : ReadData;
这样就可以让ReadEn无效时把这8个寄存器的时钟关掉。
1. 3bit的计数器插clock gating前后电路对比
插门控之前:
插门控之后:
1. 不同bit数门控时钟插入对比
SMIC.18工艺 |
|
面积 |
|
动态功耗(W) |
|
|
um2 |
门数 |
|
4bit暂存器 |
带ICG |
221.72 |
25.25 |
1.185e-05 |
|
不带ICG |
263.42 |
30 |
1.427e-05 |
3bit暂存器 |
带ICG |
175.62 |
20 |
9.160e-06 |
|
不带ICG |
197.57 |
22.5 |
9.920e-06 |
2bit暂存器 |
带ICG |
131.71 |
15 |
6.315e-06 |
|
不带ICG |
131.71 |
15 |
6.613e-06 |
1bit暂存器 |
带ICG |
85.61 |
9.75 |
3.633e-06 |
|
不带ICG |
65.86 |
7.5 |
3.307e-06 |
1. 门控时钟的结构:
a. 结构-1
This system clock gating mechanism is simple, but it is easy to make the clock after the gating incomplete and even produce glitches.
a. Structure-2
This gating method avoids the incompleteness of the gated clock and the generation of glitches, but the gated clock may generate a metastable state.
1. Structure -3
This structure solves the metastable problem of Structure -2 .
1. Structure -4
This structure with test mode can keep the clock on during the test.
1. Structure -5
When ASIC performs back-end testing, sometimes logic and registers in different clock domains may be connected for scan chain insertion. At this time, the clock source of a module may not pass its original clock path, but the entire chip The unified test clock needs to select the clock at this time.
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