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Post imitation

Post imitation

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1. Is Post-Imitation Necessary?
As the scale of a chip increases, there are a variety of voices regarding the necessity of post-imitation in IC design flow.

The reason why it is considered unnecessary is that the netlist after placement and routing can already guarantee the timing through STA, and the post-imitation is just to confirm the timing of the circuit again. And as the circuit scale continues to increase, the simulation tool's simulation speed improvement is still not obvious. Post-imitation must be a very time-consuming step, the time cost is large and the benefits are not obvious.

The reason why it is considered necessary is that, from the company's previous experience with several projects, some problems were also found in the post-imitation. For some designs, STAs cannot completely cover all paths. The post-imitation job is to implement the final check on the backend.

This article believes that with the company's current R & D strength, post-imitation is still necessary.

2. The difference between
before and after imitation: before imitation: RTL simulation

Post-imitation: gate-level simulation. Post-synthesis simulation and post-layout simulation

a. Different concerns;

Before imitation: pay attention to whether RTL is functionally correct (in accordance with design)

Post-imitation: Pay attention to whether the circuit still functions correctly under various operating conditions after the delay is inserted. 

b. Simulation objects are different;

Before imitation: the simulation object is RTL

Post-imitation: The simulation object is a gate-level netlist + SD file (may include SD of some IP)

The post-synthesis simulation uses the sdf generated by the synthesized netlist + PreSTA (no net delay, inaccurate cell delay, and inaccurate clock tree)

Post-layout simulation uses PR netlist + sdf generated by PostSTA

 

c. External incentive and response checks;

Consistent incentive and response checks used

Post-imitation may let the clock drift to simulate extreme situations

 

3. Various combinations of post-imitation
If OSC drift and three Corners are considered, the following six cases can be combined

Fast OSC + Fast SDF

Slow OSC + Fast SDF

Fast OSC + Typ SDF

Slow OSC + Typ SDF

Fast OSC + Slow SDF

Slow OSC + Slow SDF

Note: For ordinary design, you only need to consider 3 sdf. For the possible impact of osc offset (eg, flash programming), the post-imitation needs to consider the impact of more Osc offset (timing is not satisfied)

 

4. 认识sdf文件
sdf = 标准延时文件

请参考附录1中对于sdf文件的注释

 

5. Sdf反标
反标:vcs将sdf文件中的延时信息添加到门级网表中对应的地方

$sdf_annotate

例:$sdf_annotate("/home/chengp/project/zi2201/trunk/Digital/FrontEnd/sta/sdf/zi2201.20100726_v0.26_post_min_case1.eco.sdf",U_zi2201e_digital);

 

6.后仿违背的类型
a.时序器件

Setup/hold违背(posedge D -> posedge CK  , negedge D -> posedge CK)

Recovary/Removal违背 (posedge CDN -> posedge CK  ,posedge SDN -> posedge CK)

Width违背 (CK,CDN,SDN)

b.IP时序违背

IP接口时序不符合datasheet

 

7.针对违背采取的措施
a.同步处理第一级寄存器的违背

i.方法一

1,建立文件Sync.v,格式如下:

initial begin

force  Top.uXX.uYY.uZZ_reg.notifier = 1'b0;

 …………

end

2,在SimTop中的include此文件;

解决了寄存器输出为x的情况,但仿真会报很多warning

ii.方法二

1,建立文件Sync.v,格式如下

   instance {

Top.uXX.uYY.uZZ_reg,

……

   }   {noTiming}

2,在runsim文件中加入  +optconfigfile+./Sync.v

 

b.其他

i.时序约束是否存在问题

ii.时钟树是否合理

iii.电路设计是否有潜在风险

iv.接口设计是否遵循datasheet

 

8.后仿脚本
1,+neg_tchk
 

寄存器可能出现负的setup limit和hold limit。

如果sdf中存在负的setup limit或hold limit,则使用特定的规则检查

 

xb

 

xb

 

 

实际仿真结果:

 

仿真加 +neg_tchk

 

仿真调用的sdf如下图所示:

 

xb

 

a,正的setup + 负的hold

 

xb

 

 xb

 

Posedge D 发生在时钟沿前 (-2.6ns , -1.8ns)会出现setuphold违背

 

b,负的setup + 正的hold

 

 xb

 

 

 Negedge D发生在时钟沿后 ( 1.7ns , 2.9ns )会出现setuphold违背

 

2,+sdfverbose

反标过程中打印详细的信息

  

9.后仿注意的问题
1,对于一些IP的仿真模型,定义了一些延时量,但一般不针对某个corner。因此最好定义各个corner下的延时量。

 

 

 

10.  后仿遗留问题
1,反标负延时?

vcs手册中说用-negdelay可以允许sdf中的cell和net使用负延时。

实际仿真时,修改了某个cell的延时为负,仿真不加-negdelay,仿真提示:

Warning-[SDFCOM_NDI] Negative Delay Ignored

/home/chengp/project/zi2201/trunk/Digital/FrontEnd/sta/sdf/zi2201.20100726_v0.26_post_max_case1.eco.sdf, 34671

module: inv0d0, "instance: zi2201eTest.U_zi2201e_digital.U3827"

  SDF Warning: Negative delay is ignored and replaced by 0.

  Please use -negdelay to support it.

如果加-negdelay仿真,仿真提示如下:

Warning-[SDFCOM_NIOD] Negative IOPATH Delay encountered

/home/chengp/project/zi2201/trunk/Digital/FrontEnd/sta/sdf/zi2201.20100726_v0.26_post_max_case1.eco.sdf, 34671

  SDF Warning: Negative IOPATH Delay I to ZN is replaced by 0.

  This negative value cannot be handled with switch -negdelay. Please check SDF files.

 

2,+overlap作用

 

3,sdf中的mindelays ,maxdelays

 pt在使用bc_wc测例做sta分析时,生成的sdf可能mindelays和maxdelays可能不一样。如:(IOPATH I ZN (0.540::0.642) (0.302::0.362))。反标sdf时,vcs脚本中加+mindelays则反标的是0.540和0.302,加+maxdelays则反标的是0.642和0.362。

 

附录1  sdf文件 

(DELAYFILE

(SDFVERSION "OVI 2.1")

(DESIGN "zi2201_digital_virage")  // top name

(DATE "Mon Jul 26 11:06:27 2010")

(VENDOR "tsl18fs020_max")   // 生成sdf所使用的库

(PROGRAM "Synopsys PrimeTime")

(VERSION "B-2008.06-SP2") 

(DIVIDER /)

// OPERATING CONDITION "tsl18fs020_max::tsl18fs020_max"

(VOLTAGE 0.90::0.90)   // corner参数

(PROCESS "1.200::1.200")

(TEMPERATURE 125.00::125.00)

(TIMESCALE 1ns)   //延时单位

(CELL

  (CELLTYPE "zi2201_digital_virage")

  (INSTANCE)

  (DELAY

    (ABSOLUTE

    (INTERCONNECT U4384/ZN U3558/I (0.001::0.001))  // 两个cell的pin之间连线的delay

    )

  )

)

 

 

(CELL    // 网表中的每个单元的信息都是由 (CELL ..    )包括

  (CELLTYPE "inv0d0")

  (INSTANCE U3558)   // 网表中的单元

  (DELAY

    (ABSOLUTE

(IOPATH I ZN (0.540::0.642) (0.302::0.362))   // 延时数据

//          0.540= min delay from I(1->0)  to Z (0->1)

//          0.642= max delay from I(1->0)  to Z (0->1)

//          0.302= min delay from I(0->1)  to Z (1->0) 

//          0.362= max delay from I(0->1)  to Z (1->0)

    )

  )

)

 

 

(CELL

  (CELLTYPE "dfcrn1")

  (INSTANCE U_Decoder_TRCalCntH_reg_0_)

  (DELAY

    (ABSOLUTE

    (IOPATH CP QN (1.546::1.721) (1.551::1.727))

    (IOPATH CDN QN (1.907::1.907) ())

    )

  )

  (TIMINGCHECK    // timing check 参数

    (WIDTH (posedge CP) (0.532::0.532))

    (WIDTH (negedge CP) (0.972::0.972))

    (HOLD (posedge CDN) (posedge CP) (1.216::1.216))

    (RECOVERY (posedge CDN) (posedge CP) (-0.653::-0.653))

    (WIDTH (negedge CDN) (0.412::0.412))

    (SETUP (posedge D) (posedge CP) (0.219::0.219))

    (SETUP (negedge D) (posedge CP) (0.193::0.193))

    (HOLD (posedge D) (posedge CP) (-0.202::-0.202))

    (HOLD (negedge D) (posedge CP) (0.057::0.057))

  )

)

 

 

 

附录2  仿真模型
 

module inv0d0 (I,ZN);

 

output  ZN;

input   I; 

not #1 (ZN,I); 

`ifdef functional

`else

specify

// Parameter declarations

 specparam i_lh_zn_hl=-1,i_hl_zn_lh=-1;

// Delays

 (        I -=> ZN) = (i_hl_zn_lh,i_lh_zn_hl);

endspecify

`endif

 

endmodule

module dfcrn1 (D,CP,CDN,QN);

 

output  QN;

input   D,CP,CDN;

 

`ifdef neg_tchk

wire d_D,d_CP,d_CDN;

`endif

 

`ifdef functional

U_FD_P_RB #1 (QN_not,D,CP,CDN);

`else

reg notifier;

`ifdef neg_tchk

U_FD_P_RB_NO #1 (QN_not,d_D,d_CP,d_CDN,notifier);

`else

U_FD_P_RB_NO #1 (QN_not,D,CP,CDN,notifier);

`endif

`endif

 

not (QN,QN_not);

 

`ifdef functional

`else

specify

// Parameter declarations

 specparam tsu_d_h_cp=0.12,tsu_d_l_cp=0.22,tsu_cdn_h_cp=0.00,th_cp_d_h=0.00,

 th_cp_d_l=0.00,th_cp_cdn_l=0.33,tpw_cp_h=0.26,tpw_cp_l=0.43,tpw_cdn_l=0.23,

 cp_lh_qn_hl=0,cp_lh_qn_lh=0,cdn_hl_qn_lh_1=0;

// Violation constraints

`ifdef neg_tchk

 $setuphold (posedge CP &&& (CDN==1'b1),posedge D &&& (CDN==1'b1),tsu_d_h_cp,th_cp_d_l,notifier,,,d_CP,d_D);

 $setuphold (posedge CP &&& (CDN==1'b1),negedge D &&& (CDN==1'b1),tsu_d_l_cp,th_cp_d_h,notifier,,,d_CP,d_D);

 $recrem (posedge CDN,posedge CP,tsu_cdn_h_cp,th_cp_cdn_l,notifier,,,d_CDN,d_CP);

`else

 $setup (posedge D &&& (CDN==1'b1),posedge CP &&& (CDN==1'b1),tsu_d_h_cp,notifier);

 $setup (negedge D &&& (CDN==1'b1),posedge CP &&& (CDN==1'b1),tsu_d_l_cp,notifier);

 $recovery (posedge CDN,posedge CP,tsu_cdn_h_cp,notifier);

 $hold  (posedge CP &&& (CDN==1'b1),negedge D &&& (CDN==1'b1),th_cp_d_h,notifier);

 $hold  (posedge CP &&& (CDN==1'b1),posedge D &&& (CDN==1'b1),th_cp_d_l,notifier);

 $hold  (posedge CP,posedge CDN,th_cp_cdn_l,notifier);

`endif

 $width (posedge CP &&& (CDN==1'b1),tpw_cp_h,0,notifier);

 $width (negedge CP &&& (CDN==1'b1),tpw_cp_l,0,notifier);

 $width (negedge CDN,tpw_cdn_l,0,notifier);

// Delays

 if (CDN==1'b1)

 (posedge CP   => (QN -: D   )) = (cp_lh_qn_lh,cp_lh_qn_hl);

 (negedge CDN => (QN +: 1'b1)) = (cdn_hl_qn_lh_1,0);

endspecify

`endif

 

endmodule

 

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